<?xml version="1.0" encoding="UTF-8"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Yestino - The Signal · AVX2</title><link>https://yestino.com/entities/avx2-cc142b</link><description>Every event involving AVX2</description><language>en</language><atom:link href="https://yestino.com/entities/avx2-cc142b/feed.xml" rel="self" type="application/rss+xml"/><item><title>trunk/be018342370825fe89c86d51462b461591eff3d7: [caffe2/veclib] Fix (double)0 yielding -0.0 on AVX2 (#196607) (#196607)</title><link>https://yestino.com/events/trunk-be018342370825fe89c86d51462b461591eff3d7-caffe2-veclib-1f80a4</link><guid isPermaLink="true">https://yestino.com/events/trunk-be018342370825fe89c86d51462b461591eff3d7-caffe2-veclib-1f80a4</guid><pubDate>Fri, 11 Sep 2026 02:15:39 GMT</pubDate><description>Summary: Make conversion of 64-bit 0 into double be +0.0 instead of -0.0 In this way, AVX2-based i64-&gt;f64 conversion will be identical to other ISAs Test Plan:…
Sources: PyTorch Releases</description></item></channel></rss>