Change MIR to use block arguments instead of phis – LLVM Code Generation RFC
What happened
Today’s MIR/gMIR represent SSA dataflow the same way as the IR, with PHI instructions. This RFC proposes to change MIR away from PHIs, and towards block arguments, as MLIR uses. This will help make a few register allocation infrastructure problems easier for AMDGPU. With block arguments, no explicit instruction exists in successor blocks, but predecessors need to explicitly represent what it is passing to a specific…
Summary assembled by rule from the sources below