ciflow/xpu/194864: [inductor] Use Inline ASM HOP in MXFP8 nested reduction test
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- PyTorch: 118th Release in the last 90 days
- Previous: earlier the same day · trunk/335b7a63d84d579cd801d6a3afc04f04728f09eb
What happened
The MXFP8 nested-reduction test directly called the private cvt_e8m0_rceil prim, whose lowering only supports NVIDIA SM100+. This made the test fail on XPU and expanded the proposed fix into an unnecessary cross-device lowering. Use Inline ASM HOP on CUDA and ordinary tensor bit operations on XPU. This keeps the direct prim unchanged while exercising the same fused nested-reduction kernel on both backends. Test Plan…
Summary assembled by rule from the sources below