trunk/129e6f1d40be5e428a664436d97803f70aa747c0: [inductor] Enable MXFP8 nested-reduction test on XPU (#194864)
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- PyTorch: 410th Release in the last 90 days
- Previous: earlier the same day · trunk/1ee97fb52bf85376f1a9424b8f21b47e304a362f
What happened
I reviewed this AI-assisted description and confirmed it reflects the final implementation. Summary test_rmsnorm_mxfp8_scale_swizzle_kernel_form was disabled on XPU because its helper directly called the private, SM100-only cvt_e8m0_rceil prim. This change keeps that prim and its lowering unchanged. The test helper now: uses Inline ASM HOP for the SM100 E8M0 conversion on CUDA; uses ordinary tensor bit operations fo…
Summary assembled by rule from the sources below